This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-131388, filed Apr. 28, 2000, the entire contents of which are incorporated herein by reference.
The present invention relates to a level shifter applied to a decoding circuit of a semiconductor memory, e.g., a nonvolatile semiconductor memory such as an EEPROM (Electrically Erasable Programmable Read Only Memory).
A nonvolatile semiconductor memory in which data in a plurality of memory cells are simultaneously erased is called a flash memory.
FIG. 15 shows an example of the structure of a memory cell called a stacked gate memory cell applied to a nonvolatile semiconductor memory. Referring to FIG. 15, a P-well 13 is formed in an N-well 12 on a P-substrate 11. On the surface of this P-well 13, a polysilicon floating gate 17 is formed via a gate insulating film 16. A control gate 19 is formed on the floating gate 17 via an insulating film 18. A source (S) 14 and a drain (D) 15 each made of an N-impurity are formed in surface regions of the P-well 13 on the both sides of the floating gate 17 and the control gate 19.
The operation of the above memory cell will be briefly described below.
To write data in this memory cell, electrons are injected into the floating gate 17. During this injection, 6V, for example, are applied to the drain 15, 0V (ground potential) is applied to the P-well 13 (including the P-substrate 11 and the N-well 12) and the source 14, and about 10V are applied to the control gate 19. The floating gate 17 is not connected to an external power supply. Hence, the potential of this floating gate 17 is uniquely determined by the potentials of the control gate 19, the source 14, the drain 15, and the P-well 13, in accordance with the coupling ratio of the floating gate 17 to the P-well 13 and that of the floating gate 17 to the control gate 19. When the individual portions of the memory cell are thus set at these potentials, a strong lateral electric field (in the source-drain direction) is generated. In accordance with this electric field, hot electrons having high energy are generated. Some of these hot electrons are injected into the floating gate 17 over the barrier of the gate insulating film 16, writing data in the memory cell.
To erase data stored in the memory cell, electrons are withdrawn from the floating gate 17. This is done by, e.g., the following method. 10V, for example, are applied to the N-well 12, the P-well 13, and the source 14, and xe2x88x927V are applied to the control gate 19. As a consequence, a large electric field of 10 MV/cm or more is applied to the gate insulating film 16. This large electric field causes an F-N (Fowler-Noldheim) current (tunnel current) to flow through the gate insulating film 16. Accordingly, electrons are emitted from the floating gate 17 to the P-well 13 and the source 14, erasing data in the memory cell.
Data stored in the memory cell is read out as follows. As described above, the potential of the floating gate of the written memory cell differs from that of the floating gate of the erased memory cell. That is, electrons are built up in the floating gate 17 of the written memory cell. Therefore, to form an N-channel immediately below the floating gate 17 by applying a voltage to the control gate 19, the floating gate 17 must be given a positive electric charge larger than when the channel is to be formed in the erased memory cell. More specifically, the potential (to be referred to as VREAD hereinafter) of the control gate 19 is so controlled as not to form a channel in the written memory cell but to form a channel in the erased memory cell. Accordingly, by giving an appropriate potential between the drain and source and setting the potential of the control gate 19 at VREAD, e.g., 5V, a channel is formed in the erased memory cell whereas no channel is formed in the written memory cell. Consequently, an electric current determined by the potential difference between the drain and source and the potential of the floating gate flows through the erased memory cell, similar to a common N-channel transistor. Data in the memory cell can be read out by detecting whether an electric current flows through the memory cell when VREAD is thus applied to the control gate of the memory cell.
FIG. 16 shows the configuration of a nonvolatile semiconductor memory. An input circuit 21 receives an address control signal. A control circuit 22 decodes the signal from the input circuit 21 and supplies a control signal to other circuits. A memory cell array 23 has memory cells (not shown) arrayed into m rowsxc3x97n columns. A boosting circuit 24 generates a high voltage for a data write, erase, and read to the memory cells arranged in the memory cell array 23. A row decoder 25 selects a word line (not shown) arranged in the memory cell array 23, in accordance with the output signal from the control circuit 22. A column decoder 26 selects a bit line arranged in the memory cell array 23, in accordance with the output signal from the control circuit 22. A source and well decoder 27 supplies the potential of the P-well and the potential of the source to the memory cell array 23, in accordance with the output signal from the control circuit 22. A write circuit 28 performs data write and verification. A read circuit 29 discriminates data read out from a selected memory cell during data read. An output circuit 30 is connected to the read circuit 29 and outputs data read out by the read circuit 29.
FIG. 17 shows details of the arrangement of the memory cell array 23 shown in FIG. 16. For the sake of descriptive simplicity, memory cells MC are arranged into a matrix of 3 rowsxc3x974 columns in a P-well (not shown). The control gates of memory cells MC belonging to the same rows are connected to corresponding word lines WL0 to WL2. The drains of memory cells belonging to the same columns are connected to corresponding bit lines BL0 to BL3. Also, the source of each memory cell MC is connected to a source line SL, and source lines SL in the same P-well are connected together.
In data write and read, a specific memory cell is selected by a word line WLm (m=0 to 2) selected by the row decoder 25 and a bit line BLn (n=0 to 3) selected by the column decoder 26. Data write or read is performed for this selected memory cell. Data erase is performed for the mxc3x97n memory cells arranged in the same P-well at the same time.
FIG. 18 shows an example of the row decoder 25. An address converter 42 receives a plurality of row-select internal address signals 41 generated via the input circuit 21 and the control circuit 22, and activates an address-select line 45 in accordance with these internal address signals 41. The potential of the word line WLm is different from the power supply voltage (Vcc) in any of data read, write, and erase. Hence, the address-select line 45 is connected to a level shifter 43, and the potential of this address-select line 45 is converted into a required potential by the level shifter 43. The output voltage from this level shifter 43 is supplied to a buffer circuit 44. A voltage whose waveform is shaped by this buffer circuit 44 is supplied to the word line WLm.
FIG. 19 shows another example of the row decoder 25. In this example, internal address signals are divided into two systems. That is, a plurality of row-select internal address signals 41a and a plurality of row-select internal address signals 41b, generated via the input circuit 21 and the control circuit 22, are supplied to first address converters 42a and 42b, respectively. In accordance with these internal address signals 41a and 41b, the first address converters 42a and 42b activate address-select lines 45a and 45b, respectively. These address-select lines 45a and 45b are connected to level shifters 43a and 43b, respectively. These level shifters 43a and 43b convert the potentials of the address-select lines 45a and 45b into required potentials. The output voltages from the level shifter 43a and 43b are supplied to a second address converter 51. This second address converter 51 selects one of the output voltages from the first and second level shifters 43a and 43b. The output voltage from this second address converter 51 is supplied to the word line WLm via the buffer circuit 44.
FIG. 20A shows an example of the address converter 42 (including the first and second address converters 42a and 42b). This address converter 42 is an AND circuit 42c. This AND circuit 42c selects a predetermined address-select line 45 in accordance with an internal address signal.
FIG. 20B shows an example of the second address converter 51. This second address converter 51 is, e.g., an AND circuit 51a which receives a level-converted signal. For this purpose, a boosted high potential VH and a low potential VL, rather than the power supply voltage Vcc, are supplied to the AND circuit 51a. 
FIG. 20C shows an example of the buffer circuit 44. This buffer circuit 44 is composed of, e.g., two series-connected inverter circuits 44a and 44b. This buffer circuit 44 receives a level-converted signal. Therefore, the power supply voltages of the inverter circuits 44a and 44b are the high potential VH and the low potential VL.
FIG. 21 shows an example of the level shifter 43 (including 43a and 43b). This level shifter 43 comprises series-connected, high- and low-level shifters 61 and 62. The high-level shifter 61 generates a potential higher than the power supply voltage Vcc. The low-level shifter 62 generates a potential lower than a ground potential VSS. An address conversion signal is supplied as an input signal IN to the high-level shifter 61. Complementary voltages OUT and /OUT output from the high-level shifter 61 are supplied to the low-level shifter 62. The output voltage from this low-level shifter 62 is an output voltage OUT1 of the level shifter. The power supply voltages of the high-level shifter 61 are the high potential VH and the ground potential VSS. The power supply voltages of the low-level shifter 62 are the high potential VH and the low potential VL. The high-level shifter 61 outputs a signal of high potential VH and a signal of ground potential of 0V, in accordance with the Vcc-level address conversion signal. The low-level shifter 62 outputs the high potential VH or the low potential VL lower than the ground potential, in accordance with the output signal from the high-level shifter 61.
The high potential VH is set at, e.g., 5V (VREAD) in data read, at, e.g., 10V in data write, and at a predetermined potential in data erase. The level of the low potential VL is set at 0V (non-selection level) in data read, at 0V (non-selection level) in data write, and at, e.g., xe2x88x927V in data erase. These high and low potentials VH and VL are generated by the boosting circuit 24.
FIG. 22A is a circuit diagram showing an example of the high-level shifter 61. This high-level shifter 61 comprises N-channel transistors N1 and N2, P-channel transistors P1 and P2, and an inverter circuit INV. The input signal IN and an input signal /IN (not shown) inverted by the inverter INV are supplied to the gates of the N-channel transistors N1 and N2, respectively. The sources of these N-channel transistors N1 and N2 are grounded. The drains of the N-channel transistors N1 and N2 are connected to the drains and gates of the P-channel transistors P1 and P2, respectively. Also, the high potential VH is supplied to the sources of the P-channel transistors P1 and P2. The complementary output voltages OUT and /OUT are output from the nodes connecting the drains of the N-channel transistors N1 and N2 and the P-channel transistors P1 and P2, respectively.
FIG. 22B is a circuit diagram showing an example of the low-level shifter 62. This low-level shifter 62 includes N-channel transistors N3 and N4 and P-channel transistors P3 and P4. Complementary input signals, i.e., the output voltages OUT and /OUT from the high-level shifter 61 are supplied to the gates of the P-channel transistors P3 and P4, respectively. The high potential VH is supplied to the sources of these P-channel transistors P3 and P4. The drains of the P-channel transistors P3 and P4 are connected to the drains and gates of the N-channel transistors N3 and N4, respectively. The low potential VL is supplied to the sources of the N-channel transistors N3 and N4. The output signal OUT1 is output from the node connecting the drain of the N-channel transistor N4 and the drain of the P-channel transistor P4.
FIG. 23A shows the logic of the high-level shifter 61. FIG. 23B shows the logic of the low-level shifter 62.
When the input signal IN is the Vcc-level signal in the level shifter 43 shown in FIGS. 21, 22A, and 22B, the output voltage OUT from the high-level shifter 61 becomes the high potential VH, and the output signal OUT1 from the low-level shifter 62, as the output from the level shifter 43, also becomes the high potential VH.
On the other hand, when the input signal IN is 0V, the output voltage OUT from the high-level shifter 61 becomes 0V, and the output voltage OUT1 from the low-level shifter 62, as the output from the level shifter 43, becomes the low potential VL.
FIG. 24A shows the relationships between the input signal IN and the output voltages OUT and OUT1.
FIG. 24B shows the relationships between the high potential VH and the low potential VL in different operation modes, i.e., data write, read, and erase.
The level shifter shown in FIG. 21 has the following problem. That is, when a potential is supplied to a word line in accordance with an internal address signal, a predetermined potential is generated via both the high- and low-level shifters 61 and 62 in both write and read modes. This considerably lowers the speed of level conversion especially in data read required to be a high-speed operation.
It is an object of the present invention to provide a semiconductor device capable of increasing the speed of level conversion and increasing the access rate.
This object of the present invention is achieved by the following arrangement.
A semiconductor device comprising: a first level shifter having an input terminal for receiving an input signal and an output terminal, the first level shifter outputting one of a first potential and a second potential lower than the first potential from the output terminal in accordance with the level of the input signal; a second level shifter having an input terminal connected to the output terminal of the first level shifter, the second level shifter outputting one of the first potential and a third potential lower than the second potential from an output terminal in accordance with the output potential from the first level shifter; a third level shifter having an input terminal for receiving the input signal and an output terminal, the third level shifter outputting one of the first and second potentials from the output terminal in accordance with the level of the input signal; and a first switching circuit connected to the output terminals of the second and third level shifters, the first switching circuit selecting one of the output potentials from the second and third level shifters in accordance with a control signal.
Also, the present invention is achieved by the following arrangement.
A semiconductor device comprising: a first level shifter having an input terminal for receiving an input signal and an output terminal, the first level shifter outputting one of a first potential and a second potential lower than the first potential from the output terminal in accordance with the level of the input signal; a second level shifter having an input terminal connected to the output terminal of the first level shifter, the second level shifter outputting one of the first potential and a third potential lower than the second potential from an output terminal in accordance with the output potential from the first level shifter; a third level shifter having an input terminal for receiving the input signal and an output terminal, the third level shifter outputting one of the second potential and a fourth potential lower than the first potential and higher than the second potential from the output terminal in accordance with the level of the input signal; and a first switching circuit connected to the output terminals of the second and third level shifters, the first switching circuit selecting one of the output potentials from the second and third level shifters in accordance with a control signal.
Furthermore, the present invention is achieved by the following arrangement.
A semiconductor device comprising: a first level shifter having an input terminal for receiving an input signal and an output terminal, the first level shifter outputting one of a first potential and a second potential lower than the first potential from the output terminal in accordance with the level of the input signal; a second level shifter having an input terminal for receiving the input signal and an output terminal, the second level shifter outputting one of the second potential and a third potential lower than the first potential and higher than the second potential in accordance with the level of the input signal; and a first switching circuit connected to the output terminals of the first and second level shifters, the first switching circuit selecting one of the output potentials from the first and second level shifters in accordance with a control signal.
According to the semiconductor device of the present invention, the speed of level conversion can be increased and the access rate can be increased.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.